1. Field of the Invention
The invention relates generally to the field of electrical circuits and more particularly to high speed push pull circuits having speed up circuits coupled thereto.
2. Description of the Prior Art
High speed push pull circuits such as interface drivers are well known to the prior art and generally have slow rise times due to relatively high value pull up resistors and low voltages.
In each of these circuits high speed operation is desired especially when such circuits are used in memory configurations where speed of the circuit is a critical factor. However, in transistor circuits there exists various capacitances, such as stray capacitance, depletion capacitances resulting from the natural unavoidable depletions formed in the device during operation and the unavoidable interelectrode capacitances that mutually links the terminals of a transistor. Because these capacitances, hereinafter referred to collectively as the interelectrode capacitances are so significant they are disruptive and can cause uncontrolled and undesired shunting currents to be passed through transistors causing variations in the output of the circuit and subsequent losses of speed before the output voltage of the circuit is stabilized in its steady state condition.
In push pull circuits this problem caused by this interelectrode capacitance is especially acute because it can significantly delay the response of the pull down transistor and thus delay the response of the output.
In the prior art, common methods of removing this interelectrode capacitance were to apply a reverse current to the base terminal of the output transistor or to include a parallel resistor-capacitor combination in the base circuit of the transistor. Both solutions leave much to be desired and indeed in some instances it can interject additional problems into the operation of the circuit.
In U.S. Pat. No. 3,789,241 there is described a circuit for rapidly removing excess stored minority carriers from the base region of a saturated transistor and rapid charging of the interelectrode capacitance of this transistor by a pull down transistor. This patent describes a solution which is very desirable in many circuits. However, this circuit suffers the drawback that it requires additional D.C. power to the pull down transistor in order to maintain the output in a high state. Thus in circuits where D.C. power is limited such a solution is not satisfactory.
U.S. Pat. No. 3,681,619 teaches that means can be provided in electronic circuits for canceling stray direct current outputs in the circuits by means of an injected transistor feeding an impedance which connects the injected transistor to the output circuit. Again, however, although the solution depicted is desirable in some circuits, it will also require additional D.C. power to be supplied to the pull down transistor in order to maintain the output in a high state.
Both of the above described prior art solutions are therefore unsatisfactory in situations where it is necessary to achieve fast high speed stable outputs with limited D.C. power.
None of the above described prior art suggested the introduction of a speed up circuit, in such circuits, which would contribute to fast rise times of the output and virtual elimination of uncontrolled and undesired shunt currents from the output to ground through the pull down transistor that would utilize only the A.C. power of the circuit and that would not require the use of D.C. power to operate.